Large-scale quantum chip validated

A team of scientists at USC has verified that quantum effects are indeed at play in the first commercial quantum optimization processor.

The team demonstrated that the D-Wave processor housed at the USC-Lockheed Martin Quantum Computing Center behaves in a manner that indicates that quantum mechanics has a functional role in the way it works. The demonstration involved a small subset of the chip’s 128 qubits.

In other words, the device appears to be operating as a quantum processor — something that scientists had hoped for but have needed extensive testing to verify.

The quantum processor was purchased from Canadian manufacturer D-Wave nearly two years ago by Lockheed Martin and housed at the Information Sciences Institute (ISI) based at the USC Viterbi School of Engineering. As the first of its kind, the task for scientists putting it through its paces was to determine whether the quantum computer was operating as hoped.

“Using a specific test problem involving eight qubits, we have verified that the D-Wave processor performs optimization calculations [that is, finds lowest-energy solutions] using a procedure that is consistent with quantum annealing and is inconsistent with the predictions of classical annealing,” said Daniel Lidar, scientific director of the Quantum Computing Center and one of the researchers on the team. Lidar holds joint appointments at USC Viterbi and the USC Dornsife College of Letters, Arts and Sciences.

Quantum annealing is a method of solving optimization problems using quantum mechanics — at a large enough scale, potentially much faster than a traditional processor can.

Research institutions throughout the world build and use quantum processors but most only have a few quantum bits, or qubits.

Qubits have the capability of encoding the two digits of one and zero at the same time, as opposed to traditional bits, which can encode distinctly either a one or a zero. This property, called superposition, along with the ability of quantum states to “tunnel” through energy barriers, are hoped to play a role in helping future generations of the D-Wave processor to ultimately perform optimization calculations much faster than traditional processors.

With 108 functional qubits, the D-Wave processor at USC inspired hopes for a significant advance in the field of quantum computing when it was installed in October 2011 — provided it worked as a quantum information processor. Quantum processors can fall victim to a phenomenon called decoherence, which stifles their ability to behave in a quantum fashion.

The USC team’s research showed that the chip, in fact, performed largely as hoped, demonstrating the potential for quantum optimization on a larger-than-ever scale.

“Our work seems to show that, from a purely physical point of view, quantum effects play a functional role in information processing in the D-Wave processor,” said Sergio Boixo, first author of the research paper, who conducted the research while he was a computer scientist at ISI and research assistant professor at USC Viterbi.

Boixo and Lidar collaborated with Tameem Albash, postdoctoral research associate in physics at USC Dornsife; Federico Spedalieri, computer scientist at ISI; and Nicholas Chancellor, a recent physics graduate at USC Dornsife. Their findings have been published in Nature Communications.

The news comes just two months after the Quantum Computing Center’s original D-Wave processor — known commercially as the Rainier chip — was upgraded to a new 512-qubit Vesuvius chip. The computing center, which includes a magnetically shielded box that is kept frigid (near absolute zero) to protect the computer against decoherence, was designed to be upgradable to keep up with the latest developments in the field.

The new Vesuvius chip at USC is currently the only one in operation outside of D-Wave. A second such chip, owned by Google and housed at NASA’s Ames Research Center in Moffett Field, Calif., is expected to become operational later this year.

Next, the USC team will take the Vesuvius chip for a test drive, putting it through the same paces as the Rainier chip.

The research was supported by the Lockheed Martin Corp., the U.S. Army Research Office (grant number W911NF-12-1-0523), the National Science Foundation (grant number CHM-1037992), and the Army Research Office Multidisciplinary University Research Initiative (grant number W911NF-11-1-026).